aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx/synth_xilinx.cc
Commit message (Expand)AuthorAgeFilesLines
* Move dffinit til after abcEddie Hung2019-04-051-2/+2
* Merge branch 'eddie/fix_retime' into xc7srlEddie Hung2019-04-051-7/+8
|\
| * Move techamp t:$_DFF_?N? to before abc callEddie Hung2019-04-051-2/+2
| * Resolve @daveshah1 comment, update synth_xilinx helpEddie Hung2019-04-051-3/+5
| * synth_xilinx to techmap FFs after abc call, otherwise -retime failsEddie Hung2019-04-051-3/+3
* | techmap inside map_cells stageEddie Hung2019-04-051-1/+1
* | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-0/+1
|\ \
| * | Missing techmap entry in helpEddie Hung2019-04-041-0/+1
* | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-12/+12
|\| |
| * | synth_xilinx to map_cells before map_lutsEddie Hung2019-04-041-12/+12
| |/
* | t:$dff* -> t:$dff t:$dffeEddie Hung2019-04-041-2/+2
* | -nosrl meant when -nobramEddie Hung2019-04-031-1/+1
* | Disable shregmap in synth_xilinx if -retimeEddie Hung2019-04-031-3/+3
* | synth_xilinx to use shregmap with -minlen 3Eddie Hung2019-03-251-2/+2
* | Add '-nosrl' option to synth_xilinxEddie Hung2019-03-211-6/+16
* | Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-191-2/+4
|\|
| * Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
* | Cleanup synth_xilinxEddie Hung2019-03-151-2/+1
* | WorkingEddie Hung2019-03-151-7/+9
* | MisspellEddie Hung2019-03-141-1/+1
* | Revert "Add shregmap -init_msb_first and use in synth_xilinx"Eddie Hung2019-03-141-3/+2
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-141-16/+54
|\|
| * Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-051-16/+52
| |\
| | * Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-011-13/+13
| | * Modify arguments to match existing style.Keith Rothman2019-03-011-6/+6
| | * Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-011-16/+52
| * | Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
| |/
* | Add shregmap -init_msb_first and use in synth_xilinxEddie Hung2019-03-141-2/+2
* | Move shregmap until after first techmapEddie Hung2019-03-131-2/+2
* | synth_xilinx to call shregmap with enable supportEddie Hung2019-02-281-1/+1
* | synth_xilinx to use shregmap with -params tooEddie Hung2019-02-281-1/+1
* | synth_xilinx to now have shregmap call after dff2dffeEddie Hung2019-02-281-0/+2
|/
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
* xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Improving vpr output support.Tim 'mithro' Ansell2018-04-181-3/+34
* Add Xilinx RAM64X1D and RAM128X1D simulation modelsClifford Wolf2018-03-071-2/+0
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Added black box modules for all the 7-series design elements (as listed in ug...Clifford Wolf2016-03-191-0/+2
* Run dffsr2dff in synth_xilinxClifford Wolf2016-02-131-0/+2
* Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-011-2/+2
* Bugfix in Xilinx LUT mappingClifford Wolf2015-10-301-1/+1
* Added read-enable to memory modelClifford Wolf2015-09-251-2/+2
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Added output args to synth_ice40Clifford Wolf2015-05-261-2/+2
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-091-0/+12
* Added Xilinx bram black-box modulesClifford Wolf2015-04-061-0/+2
* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-041-5/+6
* Added "stat" to "synth" and "synth_xilinx"Clifford Wolf2015-02-151-0/+2
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-10 20:22:00 +0000