| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | xilinx: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -43/+27 |
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| * | xilinx: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-09 | 1 | -2/+1 |
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| * | abc9_ops: add -prep_bypass for auto bypass boxes; refactor | Eddie Hung | 2020-05-14 | 1 | -2/+0 |
| | | | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier | ||||
| * | Auto-generate .box/.lut files from specify blocks | Eddie Hung | 2020-02-27 | 1 | -3/+0 |
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| * | xilinx: Add support for LUT RAM on LUT4-based devices. | Marcin Kościelnicki | 2020-02-07 | 1 | -1/+2 |
| | | | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549 | ||||
| * | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. | Marcin Kościelnicki | 2020-02-07 | 1 | -0/+3 |
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| * | xilinx: Add support for Spartan 3A DSP block RAMs. | Marcin Kościelnicki | 2020-02-07 | 1 | -0/+1 |
| | | | | | Part of #1550 | ||||
| * | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 1 | -0/+1 |
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| * | synth_xilinx: Merge blackbox primitive libraries. | Marcin Kościelnicki | 2019-11-06 | 1 | -7/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option. | ||||
| * | xilinx: Add URAM288 mapping for xcup | David Shah | 2019-10-23 | 1 | -0/+2 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | xilinx: Add support for UltraScale[+] BRAM mapping | David Shah | 2019-10-23 | 1 | -1/+3 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | xilinx: Support multiplier mapping for all families. | Marcin Kościelnicki | 2019-10-22 | 1 | -1/+7 |
| | | | | | | This supports several older families that are not yet supported for actual logic synthesis — the intention is to add them soon. | ||||
| * | Makefile: don't assume python is called `python3` | Sean Cross | 2019-10-19 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io> | ||||
| * | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -6/+6 |
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| * | Revert "Add a xilinx_finalise pass" | Eddie Hung | 2019-09-23 | 1 | -1/+0 |
| | | | | | This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405. | ||||
| * | Add a xilinx_finalise pass | Eddie Hung | 2019-09-23 | 1 | -0/+1 |
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| * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-18 | 1 | -1/+4 |
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| | * | xilinx: Make blackbox library family-dependent. | Marcin Kościelnicki | 2019-09-15 | 1 | -1/+4 |
| | | | | | | | | | Fixes #1246. | ||||
| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-11 | 1 | -1/+2 |
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| | * | synth_xilinx: Support init values on Spartan 6 flip-flops properly. | Marcin Kościelnicki | 2019-09-07 | 1 | -1/+2 |
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| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-05 | 1 | -0/+3 |
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| | * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
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| | * | | Use abc_{map,unmap,model}.v | Eddie Hung | 2019-08-20 | 1 | -1/+3 |
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| | * | | Merge branch 'eddie/abc9_refactor' into xaig_dff | Eddie Hung | 2019-08-16 | 1 | -3/+12 |
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| | * \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-07-10 | 1 | -0/+1 |
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| | * \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-07-01 | 1 | -0/+2 |
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| | * | | | | | Wrap FDRE with $__ABC_FDRE containing comb | Eddie Hung | 2019-06-15 | 1 | -0/+1 |
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| * | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
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| | * | | | | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 |
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| * / | | | | Oops forgot these files | Eddie Hung | 2019-07-15 | 1 | -0/+1 |
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| * | | / | synth_xilinx: Initial Spartan 6 block RAM inference support. | Marcin Kościelnicki | 2019-07-11 | 1 | -3/+12 |
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| * | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-29 | 1 | -0/+2 |
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| | * | | install *_nowide.lut files | Eddie Hung | 2019-06-29 | 1 | -0/+2 |
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| * / | Revert "Remove wide mux inference" | Eddie Hung | 2019-06-14 | 1 | -0/+1 |
| |/ | | | | This reverts commit 738fdfe8f55e18ac7f315cd68c117eae370004ca. | ||||
| * | Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut} | Eddie Hung | 2019-06-14 | 1 | -2/+2 |
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| * | Remove wide mux inference | Eddie Hung | 2019-06-12 | 1 | -1/+0 |
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| * | Add mux_map.v for wide mux | Eddie Hung | 2019-06-04 | 1 | -0/+1 |
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| * | Cleanup, call pmux2shiftx even without -nosrl | Eddie Hung | 2019-04-22 | 1 | -3/+2 |
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| * | Add +/xilinx/cells_box.v containing models for ABC boxes | Eddie Hung | 2019-04-16 | 1 | -0/+1 |
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| * | Add cells.lut to techlibs/xilinx/ | Eddie Hung | 2019-04-09 | 1 | -0/+1 |
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| * | Add techlibs/xilinx/cells.box | Eddie Hung | 2019-04-09 | 1 | -0/+1 |
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| * | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 1 | -1/+2 |
| | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | Add Xilinx RAM64X1D and RAM128X1D simulation models | Clifford Wolf | 2018-03-07 | 1 | -1/+0 |
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| * | Add techlibs/xilinx/lut2lut.v | Clifford Wolf | 2017-07-10 | 1 | -0/+1 |
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| * | Added black box modules for all the 7-series design elements (as listed in ↵ | Clifford Wolf | 2016-03-19 | 1 | -0/+1 |
| | | | | | ug953) | ||||
| * | Switched to Python 3 | Clifford Wolf | 2015-08-22 | 1 | -1/+1 |
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| * | Another bugfix for ice40 and xilinx brams_init make rules | Clifford Wolf | 2015-08-16 | 1 | -1/+1 |
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| * | Fixed Makefile rules for generated share files | Clifford Wolf | 2015-08-16 | 1 | -1/+7 |
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| * | Adjust makefiles to work with out-of-tree builds | Clifford Wolf | 2015-08-12 | 1 | -6/+2 |
| | | | | | This is based on work done by Larry Doolittle | ||||
| * | Verific build fixes | Clifford Wolf | 2015-05-17 | 1 | -2/+2 |
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index : iCE40/yosys | |
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