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| * Move 'shregmap -tech xilinx' into map_cellsEddie Hung2019-04-221-17/+20
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| * Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-04-221-0/+2
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| * | Tidy up, fix for -nosrlEddie Hung2019-04-211-8/+7
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| * | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-211-2/+2
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| * | | Add commentsEddie Hung2019-04-211-0/+7
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| * | | Use new pmux2shiftx from #944, remove my old attemptEddie Hung2019-04-211-3/+8
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| * | | Call shregmap twice -- once for variable, another for fixedEddie Hung2019-04-051-8/+11
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| * | | Move dffinit til after abcEddie Hung2019-04-051-2/+2
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| * | | Merge branch 'eddie/fix_retime' into xc7srlEddie Hung2019-04-051-7/+8
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| * | | | techmap inside map_cells stageEddie Hung2019-04-051-1/+1
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| * | | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-0/+1
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| * \ \ \ \ Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-12/+12
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| * | | | | | t:$dff* -> t:$dff t:$dffeEddie Hung2019-04-041-2/+2
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| * | | | | | -nosrl meant when -nobramEddie Hung2019-04-031-1/+1
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| * | | | | | Disable shregmap in synth_xilinx if -retimeEddie Hung2019-04-031-3/+3
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| * | | | | | synth_xilinx to use shregmap with -minlen 3Eddie Hung2019-03-251-2/+2
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| * | | | | | Add '-nosrl' option to synth_xilinxEddie Hung2019-03-211-6/+16
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| * | | | | | Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
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| * | | | | | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-191-2/+4
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| * | | | | | | Cleanup synth_xilinxEddie Hung2019-03-151-2/+1
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| * | | | | | | WorkingEddie Hung2019-03-151-7/+9
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| * | | | | | | MisspellEddie Hung2019-03-141-1/+1
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| * | | | | | | Revert "Add shregmap -init_msb_first and use in synth_xilinx"Eddie Hung2019-03-141-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75.
| * | | | | | | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-141-16/+54
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| * | | | | | | | Add shregmap -init_msb_first and use in synth_xilinxEddie Hung2019-03-141-2/+2
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| * | | | | | | | Move shregmap until after first techmapEddie Hung2019-03-131-2/+2
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| * | | | | | | | synth_xilinx to call shregmap with enable supportEddie Hung2019-02-281-1/+1
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| * | | | | | | | synth_xilinx to use shregmap with -params tooEddie Hung2019-02-281-1/+1
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| * | | | | | | | synth_xilinx to now have shregmap call after dff2dffeEddie Hung2019-02-281-0/+2
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* | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-221-8/+10
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| * | | | | | | | Re-added clean after techmap in synth_xilinxClifford Wolf2019-04-221-0/+2
| | |_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | Merge branch 'master' into map_cells_before_map_lutsEddie Hung2019-04-211-11/+12
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| * | | | | | | Missing techmap entry in helpEddie Hung2019-04-041-0/+1
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| * | | | | | synth_xilinx to map_cells before map_lutsEddie Hung2019-04-041-12/+12
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* | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-201-6/+8
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| * | | | | Revert "synth_* with -retime option now calls abc with -D 1 as well"Eddie Hung2019-04-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 9a6da9a79a22e984ee3eec02caa230b66f10e11a.
| * | | | | synth_* with -retime option now calls abc with -D 1 as wellEddie Hung2019-04-101-2/+2
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| * | | | Move techamp t:$_DFF_?N? to before abc callEddie Hung2019-04-051-2/+2
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| * | | | Resolve @daveshah1 comment, update synth_xilinx helpEddie Hung2019-04-051-3/+5
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| * | | | synth_xilinx to techmap FFs after abc call, otherwise -retime failsEddie Hung2019-04-051-3/+3
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* / / / Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-121-1/+9
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* | / Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
| |/ |/| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-051-16/+52
|\ \ | | | | | | Changes required for VPR place and route in synth_xilinx
| * | Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-011-13/+13
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Modify arguments to match existing style.Keith Rothman2019-03-011-6/+6
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-011-16/+52
| |/ | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* / Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
| | | | | Then if targeting vpr map all the Xilinx specific LUTs back into generic Yosys LUTs.
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)