iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24	1	-1/+5
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*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	1	-9/+1
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*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	1	-0/+4
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*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	1	-4/+29
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*	Fixed parsing of default cases when not last case	Clifford Wolf	2013-11-18	1	-12/+16
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*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11	1	-3/+6
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*	More undef-propagation related fixes	Clifford Wolf	2013-11-08	1	-0/+4
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*	Fixed handling of power operator	Clifford Wolf	2013-11-07	1	-8/+20
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*	Fixed more extend vs. extend_u0 issues	Clifford Wolf	2013-11-07	1	-2/+2
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*	Renamed extend_un0() to extend_u0() and use it in genrtlil	Clifford Wolf	2013-11-07	1	-4/+8
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*	Fixed const folding in corner cases with parameters	Clifford Wolf	2013-11-07	1	-4/+7
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*	Fixed width detection for replicate operator	Clifford Wolf	2013-11-07	1	-0/+1
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*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07	1	-12/+22
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*	Fixed the fix for propagation of width hints for $signed() and $unsigned()	Clifford Wolf	2013-11-07	1	-5/+4
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*	Fixed propagation of width hints for $signed() and $unsigned()	Clifford Wolf	2013-11-06	1	-1/+4
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*	Additional fixes for undef propagation in concat and replicate ops	Clifford Wolf	2013-11-06	1	-0/+4
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*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06	1	-9/+60
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*	further improved early width and sign detection in ast simplifier	Clifford Wolf	2013-11-04	1	-2/+5
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*	Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT	Clifford Wolf	2013-11-03	1	-1/+1
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*	Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing ↵	Clifford Wolf	2013-11-02	1	-0/+2
\| \| \| \|	before constfold fixes)
*	Various ast changes for early expression width detection (prep for constfold ↵	Clifford Wolf	2013-11-02	1	-10/+70
\| \| \| \|	fixes)
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24	1	-3/+3
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*	Fixed width and sign detection for ** operator	Clifford Wolf	2013-08-19	1	-3/+3
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*	Added support for "2**n" shifter encoding	Clifford Wolf	2013-08-12	1	-0/+4
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*	Added $div and $mod technology mapping	Clifford Wolf	2013-08-09	1	-1/+1
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*	More fixes in ternary op sign handling	Clifford Wolf	2013-07-12	1	-0/+3
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*	Fixed sign handling in ternary operator	Clifford Wolf	2013-07-12	1	-2/+2
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*	Another vloghammer related bugfix	Clifford Wolf	2013-07-11	1	-1/+1
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*	Fixed sign propagation in bit-wise operators	Clifford Wolf	2013-07-09	1	-0/+1
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*	More fixes in ast expression sign/width handling	Clifford Wolf	2013-07-09	1	-9/+8
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*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	1	-33/+163
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*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07	1	-1/+1
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*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-0/+1
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*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13	1	-4/+2
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*	Sign-extension related fixes in SatGen and AST frontend	Clifford Wolf	2013-06-10	1	-0/+2
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*	Fixes and improvements in AST const folding	Clifford Wolf	2013-06-10	1	-1/+1
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*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	1	-3/+9
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*	Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵	Clifford Wolf	2013-04-13	1	-4/+4
\| \| \| \|	as case values
*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31	1	-5/+15
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*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	1	-1/+3
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*	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26	1	-0/+1
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*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25	1	-3/+5
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*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	1	-1/+1
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+1054