| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | Add comments | Eddie Hung | 2019-04-21 | 1 | -0/+7 | |
| | * | | | Use new pmux2shiftx from #944, remove my old attempt | Eddie Hung | 2019-04-21 | 1 | -3/+8 | |
| | * | | | Call shregmap twice -- once for variable, another for fixed | Eddie Hung | 2019-04-05 | 1 | -8/+11 | |
| | * | | | Move dffinit til after abc | Eddie Hung | 2019-04-05 | 1 | -2/+2 | |
| | * | | | Merge branch 'eddie/fix_retime' into xc7srl | Eddie Hung | 2019-04-05 | 1 | -7/+8 | |
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| | * | | | | techmap inside map_cells stage | Eddie Hung | 2019-04-05 | 1 | -1/+1 | |
| | * | | | | Merge branch 'map_cells_before_map_luts' into xc7srl | Eddie Hung | 2019-04-04 | 1 | -0/+1 | |
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| | * \ \ \ \ | Merge branch 'map_cells_before_map_luts' into xc7srl | Eddie Hung | 2019-04-04 | 1 | -12/+12 | |
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| | * | | | | | | t:$dff* -> t:$dff t:$dffe | Eddie Hung | 2019-04-04 | 1 | -2/+2 | |
| | * | | | | | | -nosrl meant when -nobram | Eddie Hung | 2019-04-03 | 1 | -1/+1 | |
| | * | | | | | | Disable shregmap in synth_xilinx if -retime | Eddie Hung | 2019-04-03 | 1 | -3/+3 | |
| | * | | | | | | synth_xilinx to use shregmap with -minlen 3 | Eddie Hung | 2019-03-25 | 1 | -2/+2 | |
| | * | | | | | | Add '-nosrl' option to synth_xilinx | Eddie Hung | 2019-03-21 | 1 | -6/+16 | |
| | * | | | | | | Restore original synth_xilinx commands | Eddie Hung | 2019-03-19 | 1 | -1/+2 | |
| | * | | | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-19 | 1 | -2/+4 | |
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| | * | | | | | | | Cleanup synth_xilinx | Eddie Hung | 2019-03-15 | 1 | -2/+1 | |
| | * | | | | | | | Working | Eddie Hung | 2019-03-15 | 1 | -7/+9 | |
| | * | | | | | | | Misspell | Eddie Hung | 2019-03-14 | 1 | -1/+1 | |
| | * | | | | | | | Revert "Add shregmap -init_msb_first and use in synth_xilinx" | Eddie Hung | 2019-03-14 | 1 | -3/+2 | |
| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-14 | 1 | -16/+54 | |
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| | * | | | | | | | | Add shregmap -init_msb_first and use in synth_xilinx | Eddie Hung | 2019-03-14 | 1 | -2/+2 | |
| | * | | | | | | | | Move shregmap until after first techmap | Eddie Hung | 2019-03-13 | 1 | -2/+2 | |
| | * | | | | | | | | synth_xilinx to call shregmap with enable support | Eddie Hung | 2019-02-28 | 1 | -1/+1 | |
| | * | | | | | | | | synth_xilinx to use shregmap with -params too | Eddie Hung | 2019-02-28 | 1 | -1/+1 | |
| | * | | | | | | | | synth_xilinx to now have shregmap call after dff2dffe | Eddie Hung | 2019-02-28 | 1 | -0/+2 | |
| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 1 | -8/+10 | |
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| | * | | | | | | | | Re-added clean after techmap in synth_xilinx | Clifford Wolf | 2019-04-22 | 1 | -0/+2 | |
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| | * | | | | | | | Merge branch 'master' into map_cells_before_map_luts | Eddie Hung | 2019-04-21 | 1 | -11/+12 | |
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| | * | | | | | | | Missing techmap entry in help | Eddie Hung | 2019-04-04 | 1 | -0/+1 | |
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| | * | | | | | | synth_xilinx to map_cells before map_luts | Eddie Hung | 2019-04-04 | 1 | -12/+12 | |
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| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-20 | 1 | -6/+8 | |
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| | * | | | | | Revert "synth_* with -retime option now calls abc with -D 1 as well" | Eddie Hung | 2019-04-18 | 1 | -2/+2 | |
| | * | | | | | synth_* with -retime option now calls abc with -D 1 as well | Eddie Hung | 2019-04-10 | 1 | -2/+2 | |
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| | * | | | | Move techamp t:$_DFF_?N? to before abc call | Eddie Hung | 2019-04-05 | 1 | -2/+2 | |
| | * | | | | Resolve @daveshah1 comment, update synth_xilinx help | Eddie Hung | 2019-04-05 | 1 | -3/+5 | |
| | * | | | | synth_xilinx to techmap FFs after abc call, otherwise -retime fails | Eddie Hung | 2019-04-05 | 1 | -3/+3 | |
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| * / / / | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-12 | 1 | -1/+9 | |
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| * | / | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 | Clifford Wolf | 2019-03-19 | 1 | -2/+4 | |
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| * | | Merge pull request #842 from litghost/merge_upstream | Clifford Wolf | 2019-03-05 | 1 | -16/+52 | |
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| | * | | Use singular for disabling of DRAM or BRAM inference. | Keith Rothman | 2019-03-01 | 1 | -13/+13 | |
| | * | | Modify arguments to match existing style. | Keith Rothman | 2019-03-01 | 1 | -6/+6 | |
| | * | | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 1 | -16/+52 | |
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| * / | Use "write_edif -pvector bra" for Xilinx EDIF files | Clifford Wolf | 2019-03-05 | 1 | -1/+1 | |
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| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -1/+1 | |
| * | xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. | Tim 'mithro' Ansell | 2018-10-08 | 1 | -3/+2 | |
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 | |
| * | Improving vpr output support. | Tim 'mithro' Ansell | 2018-04-18 | 1 | -3/+34 | |
| * | Add Xilinx RAM64X1D and RAM128X1D simulation models | Clifford Wolf | 2018-03-07 | 1 | -2/+0 | |
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 | |
| * | Added black box modules for all the 7-series design elements (as listed in ug... | Clifford Wolf | 2016-03-19 | 1 | -0/+2 | |
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index : iCE40/yosys | |
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